Ashwood architecture (multi-core memory)

Ashwood architecture is a multi-core memory system that works by integrating smart controller circuitry next to the memory array on a single chip, providing parallel access to the array for hundreds of concurrent processes, thereby increasing throughput and lowering average access time.

Ashwood architecture was developed by cryptographer Joseph Ashwood, who claims his design “borrows extensively from today’s modern multi-core CPUs and shares some features with Fibre Channel.” (source)

According to Ashwood, his architecture provides parallel access to bit cells on memory chips, breaking the serial bottleneck that is strangling non-volatile storage media like flash, with an architecture that can be applied to any memory chip bit cell.

See also multi-core technology.

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